1. Field
Embodiments of the invention relate to electronic devices, and more particularly, to input bias current cancellation circuits.
2. Description of the Related Technology
An operational amplifier or an instrumentation amplifier can have one or more bipolar input transistors having an input bias current. The input bias current and associated current noise can be often higher than would be desired. The input current noise can be introduced at the input of the input transistors and amplified subsequently, thereby adversely affecting the operation of the amplifier.
In certain instances, an amplifier can have an input bias current cancellation circuit to cancel its input bias current. The input bias current cancellation circuit can generate a reference current in a manner similar to that causing the input bias current. The reference current can be mirrored to form an input bias cancellation current, which can be received by the input transistors, thereby canceling the input bias current.
However, input current noise is not cancelled by the input bias current cancellation circuit because the input bias cancellation current noise is not correlated to the input bias current noise. Rather, the input bias current cancellation circuit can actually have the undesirable side effect of increasing the input current noise.
Description of FIGS. 1, 2A and 2B
FIG. 1 is a schematic block diagram illustrating a conventional amplification circuit 100 that includes a bipolar input differential pair 9 and an input bias current cancellation circuit 6. The differential pair 9 forms an input stage, and can include a first input transistor 1 and a second input transistor 2. The illustrated transistors 1, 2 are NPN bipolar transistors, each of which has an emitter, a base, and a collector. In other instances, each of the transistors 1, 2 can be PNP bipolar transistors. In certain instances, the amplification circuit can further include additional transistors to form the input stage.
The differential pair 9 can be biased for desired amplifier performance with a tail current source 3. The current of the tail current source 3 can be selected so as to, for example, place the input transistors 1, 2 in the forward-active region. For purposes of illustration only, the tail current source 3 can be referred to as having a current value of “IT” hereinafter. Skilled artisans will recognize that the current value IT can be selected from a multitude of values, depending on a variety of circuit design constraints and factors.
As illustrated in FIG. 1, a positive terminal 4 and a negative terminal 5 can be electrically connected to the bases of the input transistors 1, 2, respectively. Even when no input signal is applied to the positive and negative terminals 4, 5, base currents can flow in the first and second input transistors 1, 2 as a result of the biasing provided by the tail current source 3.
In order to prevent an input bias current from being drawn from the positive and negative terminals 4, 5, the input bias current cancellation circuit 6 can supply the bias currents of the first and second input transistors 1, 2. In particular, the input bias current cancellation circuit 6 can be configured to produce a first cancellation current I1 and a second cancellation current I2 having a magnitude substantially equal to that of the base bias currents of the first and second input transistors 1, 2. When the input transistors 1, 2 are substantially identical and have a common-emitter current gain of beta (“β”), the input transistors 1, 2 have base bias currents of about IT/2β. Accordingly, the first and second cancellation currents I1, I2 can be configured to have a value of about IT/2β, so as to substantially provide the base bias currents of the input transistors 1, 2.
FIG. 2A illustrates a bipolar differential pair 9 provided with a conventional input bias current cancellation circuit 6. The input bias current cancellation circuit 6 is electrically connected to the bipolar differential pair 9 having first and second input transistors 1, 2, which receive positive and negative inputs 4, 5, respectively. The input transistors 1, 2 are biased by a tail current source 3, as described earlier in connection with FIG. 1. The input bias current cancellation circuit 6 can provide first and second cancellation currents I1, I2 to substantially cancel the input bias currents of the input transistors 1, 2. The illustrated input bias current cancellation circuit 6 includes a reference current source 10, a reference transistor 11, a diode 12, a first mirror transistor 13, and a second mirror transistor 14. The illustrated input bias current cancellation circuit 6 is connected to a first voltage reference V1 and a second voltage reference V2.
The reference transistor 11 can be biased with the reference current source 10 having a current value of about IT/2, which is substantially equal to the bias current received by each of the input transistors 1, 2. Additionally, the reference transistor 11 can be chosen to be substantially identical to the first and second input transistors 1, 2 so that all three of the transistors have substantially identical transistor geometries and properties. Accordingly, the base current IrefB of the reference transistor 11 and the base bias currents of the first and second input transistors 1, 2 can also be substantially equal, and can have a value of about IT/2β. Thus, the base current IrefB of the reference transistor 11 can be mirrored to produce the first and second cancellation currents I1, I2.
The base current IrefB of the reference transistor 11 can be mirrored in a variety of ways. In the illustrated example, mirroring can be accomplished using the diode 12, the first mirror transistor 13, and the second mirror transistor 14, which are collectively referred to as a current mirror 16. As shown in FIG. 2A, the first and second mirror transistors 13, 14 can be PNP bipolar transistors, each having a PN junction between the emitter and base nodes. As skilled artisans will recognize, the bias current through the diode 12 creates a voltage across the diode 12, which can be placed across the emitter and base nodes of the first and second mirror transistors 13, 14. By biasing the base-emitter voltages of the first and second mirror transistors 13, 14 in this manner, the input bias current cancellation circuit 6 can provide the first and second cancellation currents I1, I2, each having a value of about IT/2β.
While canceling the input bias currents, the input bias current cancellation circuit 6 can increase input current noise significantly. For example, the shot noise of a bipolar transistor having a base current of IB has a mean square value in2 of about 2qIBΔf, where q is the magnitude of the electrical charge on an electron and Δf is the frequency band of interest in the amplifier. Thus, the base current of the transistor 1 (or the transistor 2) can have mean square shot noise when biased at IT/2β equal to about qITΔf/β. Neglecting the noise in the current mirror 16, which can typically be quite small, the noise in the first and second cancellation currents I1, I2 has a mean square value equal to about the shot noise in the base current IrefB, or qITΔf/β. The noise in the first and second cancellation currents I1, I2 is added to the noise of the base currents of the input transistors 1, 2 to produce the overall input current noise. The noise from the input bias current cancellation circuit 6 and the noise in the base currents of the input transistors 1, 2 are typically uncorrelated, and thus the conventional input bias current cancellation circuit 6 increases the overall root mean square (“rms”) input current noise by a factor of √2.
FIG. 2B illustrates a bipolar differential pair 9 having an input bias current cancellation circuit 19. As will be described below, the reduced input current noise relative to the circuit illustrated in FIG. 2A comes at the expense of increased power consumption. The illustrated input bias current cancellation circuit 19 includes a reference current source 20, a reference transistor 21, a diode 22, a first mirror transistor 23, and a second mirror transistor 24. As shown in FIG. 2B, the reference current source 20 has a current value of N*IT/2, where N is selected to be greater than 1 to reduce input bias current noise, as will be described below.
As shown in FIG. 2B, the current of the reference current source 20 can be increased relative to the current of the reference current source 10 of FIG. 2A by a factor of N. Additionally, the geometries of the illustrated reference transistor 21 and diode 22 can likewise be increased by a factor of N relative to the geometries of the reference transistor 11 and diode 12 of FIG. 2A.
The first mirror transistor 23 and the second mirror transistor 24 can have geometries similar to those of the first and second mirror transistors 13, 14 of FIG. 2A. However, the size of the diode 22 relative to the first and second mirror transistors 23, 24 is selected to be about N times greater so as to form a current mirror having an attenuation factor of N. Thus, the cancellation currents I1, I2 can substantially match with the input bias currents to the transistors 1, 2.
By increasing the current of the reference current source 20 relative to that shown in FIG. 2A, the overall noise in the first and second cancellation currents I1, I2 can be reduced, thereby reducing the overall input current noise. Although increasing the current of the reference current source 20 increases the noise of the base current IrefB, the noise of the base current IrefB increases only in proportion to the square root of the reference source current, since the shot noise of a bipolar transistor having a base current of IB has a theoretical mean square value in2 of 2qIBΔf. However, the current mirror attenuates the noise proportionally. The noise of the current IrefB is increased by a factor of √N, but the current mirror 16 attenuates the current noise by a factor of N. Accordingly, increasing the current of the reference current source 20 reduces the rms input current noise caused by the input bias current cancellation circuit 6 by a factor of √N. However, the reduction in noise comes at the cost of increased power consumption.
Increasing the current of the reference current source 20 can increase overall power consumption considerably. In low-noise amplifiers, IT can be, for example, in the milliamp range, and therefore it may not be feasible to increase the current of the reference current source 20.